Sample Problem Solutions from the Annual International Microelectronics Olympiad of Armenia

Problem 1.

The same current flows through both transistors. Vx<4V, the transistor below is not saturated VDS<VGS-VT, and the one above is saturated VDS=VGS=5-Vx.

Problem 1. a

Solving these equations, for example graphically, the following will be obtained Vx=1.09V. Taking W/L=1 result can be calculated.
Problem 1. b

Problem 2.

a. A = (CL/Cin1)1/N
(W/L)1=1, (W/L)2=12.6, (W/L)2=158.7

b. N=ln(CL/Cin1)= ln(20∙103/10)=7.6
(W/L)1=1, (W/L)2=A2,…, (W/L)7=A7
c. P=VDD2F Cin1Σ(A+A2+..+A7)

Problem 3.

Let F1 be the fault "line A stuck-at-1", F2 be "line B stuck-at-1" and F3 be "line Z* be stuck-at-1". Then it is easy to check that F1 = F2 = F3 since F1={(00)}, F2={(00)}, F3={(00)}.

Problem 4.

1. S1 = 0; S2 = 1; S3= 0;
2. S1 = 1; S2 = 1; S3= 0;
3. S1 = x; S2 = x; S3= 1;
4. S1 = x; S2 = 0; S3= 0;

Verilog description of the circuit:

module task_1(data, clk, S1,S2, S3, reset, out);
   input data, clk, S1,S2, S3, reset;
   output out, q1, q2, q3;
always @(posedge clk)
   if (reset==0) q1=0; //synchronous reset
   else if (S1==1) q1=q1^data;//T flip-flop
   else q1=data;      //D-flip-flop
always @ (data or q1)
   if (S2) q3=q1;
   else q3=data;
always @ (clk or data)
   if (clk) q2=data;
   else q2=q2;
always @(q2 or q3)
   if (S3) out=q2;
   else out = q3;

Problem 5.

assign data_out[1] = data_in[2] | data_in[3] | data_in[6] | data_in[7];

Problem 6.

Problem 6.

Problem 7.

The saturation voltage of the transistor VDS sat.=VGS–Vt=3-1=2V.
VDS>VDS sat therefore the transistor operates in saturation mode.
In this mode the drain current of the transistor will equal ID=0,5 μn, Cox (W/L) (VGS-Vt)2.
Calculate Cox=(Ɛ0Ɛsi o2)/tox=(3,9x8,85x10-14)/10x10-7=3,45x10-7F/cm2.
ID=0,5x300x3,45x10-7(3-1)2x (10/1)=2,07uA.
Transconductance gm=d ID/d VGS
gm= μn Cox (W/L) (VGS-Vt)=300x3,45x10-7x10x2= 2uA
Answer: 2,07uA and 2uA.

Problem 8.

Problem 8.

Search strategy is the following:
1) Starting from the 2nd vertex, go deeper in any path as it is still possible.
2) Return by searching other paths.
3) Repeat the 1st and the 2nd steps until detecting all possible vertices.
4) If there are still undetected vertices, select one of them and repeat 1-3 steps.
5) Repeat 1-4 steps until detecting all the vertices of the graph.
Mark the numbers of detection and completion steps on vertices.

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